1. Technical Field
This invention relates to computer processors and, more particularly, to multi-ported memory devices for use in such processors.
2. Discussion
Very long instruction word (VLIW) and super-scalar processor techniques for very high performance computer processors require multi-ported register files to support multiple function unit concurrency. VLIW and super-scalar make up two of the three leading techniques (the other being super-pipelining) currently being used to extend the performance of high-end, state of the art microprocessors. VLIW and super-scalar extend uni-processor performance by executing more than one function/operation per clock. The current standard approach to support the concurrency is to feed the operands to multiple function units, and write the results back, to a multi-ported register file. The ports of the register file are dedicated to specific functional units. For example, the Intel iWarp processor dedicates specific ports to the input and outputs of the functional units (integer, floating point multiplier, and floating point ALU) and uses special hardwired memory locations and ports to implement the specialized interconnections to the stream gates and local memory unit. The iWarp 's use of dedicated ports brings the total number of effective ports to 9 read and 6 write ports. Matsushita's newest microprocessor, the Ohmega processor, uses a six port multi-ported register file with dedicated read and write ports. The Ohmega processor is a super-scalar processor. Its floating point register file is connected to a floating point ALU (2 read and 1 write) and a floating point multiplier (2 read and 1 write). Similarly, the addressing function units are connected to dedicated ports of a six port (integer) register file. Weitek's newest floating point processor, the W4164, is based on an eight ported register file. The ports are dedicated to specific function units: multiplier/divider 2 read, 1 write, floating point ALU 2 read, 1 write, and a processor read End write port.
The dedicated memory port approach is a wasteful use of resources because typical instruction usage does not use all available ports simultaneously. Extra ports require increased chip complexity and cost. Extra memory ports also reduce the speed of the memory (and possibly the processor). Prior microcoded processors that used limited port sharing had processor instructions that encoded not only the address of the registers that needed to be read or written but also encoded the information of which port to use (multiplexer selects).
The present invention is directed to solving one or more of these problems.